Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
98dd329c028fec285730d65e09a31eaf63609ccb
/
.
/
src
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sat_set_assumes.ys
blob: 690e0556177b8ef330ab37891833104ba8044253 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
proc
tee
-
o result
.
log sat
-
set
-
assumes middle