Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
98dd329c028fec285730d65e09a31eaf63609ccb
/
.
/
src
/
Testcases
/
YosysTests
/
simple
/
scripts
/
shregmap_init.ys
blob: bb0752eba4b3d773c3d249b95bc2343bc169ca2d [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
synth_greenpak4
-
run
begin
:
map_luts
shregmap
-
init
design
-
reset
read_verilog
../
top
.
v
write_verilog synth
.
v