SVIncCompil/Testcases/YosysTests/regression/issue_01225/top.v - third_party/Surelog - Git at Google

 module top(inout pin, input dout, sel, output din);
 assign pin = sel ? dout : 1'bz;
 assign din = pin;
 endmodule
	module top(inout pin, input dout, sel, output din);
	assign pin = sel ? dout : 1'bz;
	assign din = pin;
	endmodule