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foss-fpga-tools
/
third_party
/
Surelog
/
9f7b36873a88874b623e3f6e6f0e5bb65ac3c273
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00071
/
top.v
blob: 43132065a9138e4efb09ae28af1920412a59f52b [
file
]
module
top
(
b
,
c
);
input b
;
output c
;
assign c
=
b
;
endmodule
