SVIncCompil/Testcases/YosysOldTests/sasc/YosysOldSasc.log

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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0101] rtl/sasc_brg.v:66 Cannot open include file "timescale.v".

[ERROR:PP0101] rtl/sasc_fifo4.v:60 Cannot open include file "timescale.v".

[ERROR:PP0101] rtl/sasc_top.v:62 Cannot open include file "timescale.v".

[WARNI:PA0205] cache/synth.v:1 No timescale set for "sasc_fifo4".

[WARNI:PA0205] cache/synth.v:282 No timescale set for "sasc_top".

[WARNI:PA0205] timescale.v:22 No timescale set for "sasc_brg".

[INFO :CP0300] Compilation...

[INFO :CP0303] cache/synth.v:1 Compile module "work@sasc_fifo4".

[INFO :CP0303] timescale.v:22 Compile module "work@sasc_brg".

[INFO :CP0303] cache/synth.v:282 Compile module "work@sasc_top".

[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout",
there are 2 more instances of this message.

[NOTE :CP0309] cache/synth.v:282 Implicit port type (wire) for "dout_o",
there are 2 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] cache/synth.v:282 Top level module "work@sasc_top".

[NOTE :EL0503] timescale.v:22 Top level module "work@sasc_brg".

[NOTE :EL0504] Multiple top level modules in design.

[NOTE :EL0508] Nb Top level modules: 2.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 4.

[NOTE :EL0511] Nb leaf instances: 3.

[  FATAL] : 0
[  ERROR] : 3
[WARNING] : 3
[   NOTE] : 9

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*   End SURELOG SVerilog Compiler/Linter   *
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3.34user 0.06system 0:01.81elapsed 187%CPU (0avgtext+0avgdata 59968maxresident)k
0inputs+152outputs (0major+12347minor)pagefaults 0swaps