Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
9feee6fe73aa5195cb7e9a2bf9ab3c6a3ff0980d
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
architecture
/
ice40_wrapcarry
/
top.v
blob: d3a9e642667d637366a8c89e57bf3d0f3da07c0a [
file
] [
log
] [
blame
]
module
top
(
input
[
3
:
0
]
x
,
input
[
3
:
0
]
y
,
output
[
3
:
0
]
A
,
output
[
3
:
0
]
B
);
assign B
=
x
/
y
;
endmodule
