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foss-fpga-tools
/
third_party
/
Surelog
/
a50fc0da15e88d7b685f92dc843d3d71b716c8a4
/
.
/
src
/
Testcases
/
Icarus
/
ivltests
/
busbug.v
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module
busbug
();
reg x
,
y
,
z
;
initial
begin
x
=
1
'b0;
y=1'
b0
;
z
=
1
'b1;
$display("%b%b=%b",
x ^ y, x ^ (y ^ z),
{x ^ y, x ^ (y ^ z)}
);
end
endmodule