Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
a50fc0da15e88d7b685f92dc843d3d71b716c8a4
/
.
/
src
/
Testcases
/
Yosys
/
lut
/
map_mux.v
blob: ae69404e2854a4f6191b709b7a6c7cb76256d0a5 [
file
] [
log
] [
blame
]
module
top
();
input a
,
b
,
s
;
output y
;
assign y
=
s
?
a
:
b
;
endmodule