src/Testcases/YosysTestSuite/various/equiv_opt_multiclock.ys - third_party/Surelog - Git at Google

 read_verilog <<EOT
 module top(input clk, pre, d, output reg q);
 	always @(posedge clk, posedge pre)
 		if (pre)
 			q <= 1'b1;
 		else
 			q <= d;
 endmodule
 EOT

 prep
 equiv_opt -assert -multiclock -map +/simcells.v synth
	read_verilog <<EOT
	module top(input clk, pre, d, output reg q);
	always @(posedge clk, posedge pre)
	if (pre)
	q <= 1'b1;
	else
	q <= d;
	endmodule
	EOT

	prep
	equiv_opt -assert -multiclock -map +/simcells.v synth