src/Testcases/YosysTests/simple/scripts/expose_input.ys - third_party/Surelog - Git at Google

 read_verilog ../top.v
 synth -top top
 expose -input
 proc
 flatten
 opt
 opt_rmdff
 expose -input
 design -reset
 read_verilog ../top.v
 synth -top top
 write_verilog synth.v
	read_verilog ../top.v
	synth -top top
	expose -input
	proc
	flatten
	opt
	opt_rmdff
	expose -input
	design -reset
	read_verilog ../top.v
	synth -top top
	write_verilog synth.v