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foss-fpga-tools
/
third_party
/
Surelog
/
a50fc0da15e88d7b685f92dc843d3d71b716c8a4
/
.
/
src
/
Testcases
/
YosysTests
/
simple
/
scripts
/
submod_mem.ys
blob: 5c09e8b9be3fa30a0fe1c7385dc2aebfffc96a77 [
file
]
read_verilog
../
top
.
v
memory_memx
proc
submod
design
-
reset
read_verilog
../
top
.
v
synth
-
top top
write_verilog synth
.
v
