| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
| |
| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
| |
| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
| |
| [ERROR:PP0101] rtl/pcm_slv_top.v:65 Cannot open include file "timescale.v". |
| |
| [WARNI:PA0205] cache/synth.v:1 No timescale set for "pcm_slv_top". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] cache/synth.v:1 Compile module "work@pcm_slv_top". |
| |
| [NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout_o". |
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| [INFO :EL0526] Design Elaboration... |
| |
| [NOTE :EL0503] cache/synth.v:1 Top level module "work@pcm_slv_top". |
| |
| [WARNI:EL0505] timescale.v:11 Multiply defined module "work@pcm_slv_top", |
| cache/synth.v:1 previous definition. |
| |
| [NOTE :EL0508] Nb Top level modules: 1. |
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| [NOTE :EL0509] Max instance depth: 1. |
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| [NOTE :EL0510] Nb instances: 1. |
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| [NOTE :EL0511] Nb leaf instances: 1. |
| |
| [ FATAL] : 0 |
| [ ERROR] : 1 |
| [WARNING] : 2 |
| [ NOTE] : 6 |
| |
| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
| |
| 1.23user 0.03system 0:00.85elapsed 148%CPU (0avgtext+0avgdata 44116maxresident)k |
| 64inputs+112outputs (0major+12305minor)pagefaults 0swaps |
