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| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
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| Copyright (c) 2017-2019 Alain Dargelas, |
| http://www.apache.org/licenses/LICENSE-2.0 |
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| VERSION: 1.00 |
| BUILT : Nov 13 2019 |
| DATE : 2019-11-13.17:07:20 |
| COMMAND: -writepp -parse -mt max -nopython -fileunit cache/synth.v rtl/pcm_slv_top.v rtl/timescale.v +incdir+. -nobuiltin -nocache |
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| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
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| [ERROR:PP0101] rtl/pcm_slv_top.v:65 Cannot open include file "timescale.v". |
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| [WARNI:PA0205] cache/synth.v:1 No timescale set for "pcm_slv_top". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] cache/synth.v:1 Compile module "work@pcm_slv_top". |
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| [NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout_o". |
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| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] cache/synth.v:1 Top level module "work@pcm_slv_top". |
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| [WARNI:EL0505] timescale.v:11 Multiply defined module "work@pcm_slv_top", |
| cache/synth.v:1 previous definition. |
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| [NOTE :EL0508] Nb Top level modules: 1. |
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| [NOTE :EL0509] Max instance depth: 1. |
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| [NOTE :EL0510] Nb instances: 1. |
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| [NOTE :EL0511] Nb leaf instances: 1. |
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| [ FATAL] : 0 |
| [ ERROR] : 1 |
| [WARNING] : 2 |
| [ NOTE] : 6 |
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| * End SURELOG SVerilog Compiler/Linter * |
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