blob: 56d6c87ea5387be57f4e3d7b587e6aae8f96e190 [file] [log] [blame]
Skipping large tests
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START SURELOG REGRESSION
Starts on 11/13/2019 22:27:19
COMMAND: /usr/bin/time /home/alain/Surelog/SVIncCompil/Testcases/../dist/surelog/surelog
Creating release for regression...
Skipping ovm_pkg...
Skipping uvm_pkg...
Created dist/surelog_release_tcmalloc.tar.gz
PASS: surelog_release_tcmalloc
THERE ARE 103 tests
RUNNING 1 tests
+--------------+----------+----------+----------+----------+----------+----------+--------------+--------------+
| TESTNAME | STATUS | FATALS | ERRORS | WARNINGS | NOTES | SYNTAX | ELAPSED TIME | MEM(Mb) |
+--------------+----------+----------+----------+----------+----------+----------+--------------+--------------+
cd SimpleClass1
/usr/bin/time /home/alain/Surelog/SVIncCompil/Testcases/../dist/surelog/surelog +incdir+.+../../../UVM/uvm-1.2/src/ ../../../UVM/uvm-1.2/src/uvm_pkg.sv -writepp -parse -d inst -mt max top.v
| SimpleClass1 | PASS | 0 | 8 | 15 | 8 | 0 | 2s (+1s) | 115 |
+--------------+----------+----------+----------+----------+----------+----------+--------------+--------------+
RESULT : PASS
+--------------+----------+----------+
| | CURRENT | PREVIOUS |
+--------------+----------+----------+
|TOTAL ELAPSED | 2s | 1s |
|TOTAL USER | 2s | 1s |
|MAX MEM TEST | 115Mb | 115Mb |
|MAX TIME TEST | 2s | 1s |
+--------------+----------+----------+
End on 11/13/2019 22:27:25
END SURELOG REGRESSION
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