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foss-fpga-tools
/
third_party
/
Surelog
/
b2c8950dbc163e2320c742c5badef8d829b836c0
/
.
/
SVIncCompil
/
Testcases
/
Yosys
/
errors
/
syntax_err07.v
blob: 62bcc6b3ed9ebb51f419c1cbaa088ecce85243fd [
file
]
module
a
;
wire
[
5
:
0
]
x
;
wire
[
3
:
0
]
y
;
assign y
=
(
4
)
55
;
endmodule
