Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
b2c8950dbc163e2320c742c5badef8d829b836c0
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
mutate_const1.ys
blob: 80d5d5e6f7e39afe6fc73ea2101572157063d6e3 [
file
]
read_verilog
../
top
.
v
tee
-
o result
.
log mutate
-
mode const1
-
module
top
-
cell $add$
../
top
.
v
:
12
$2
-
port Y
-
portbit
0
-
wire A
-
wirebit
0
-
src
../
top
.
v
:
7
-
src
../
top
.
v
:
12
tee
-
o result
.
log
dump
