Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
b2c8950dbc163e2320c742c5badef8d829b836c0
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sim_reset.ys
blob: b45f0ec32d98c55df2c72ad479ebb8f13eb46b48 [
file
]
read_verilog
../
top
.
v
proc
tee
-
o result
.
log sim
-
reset we_b top
