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foss-fpga-tools
/
third_party
/
Surelog
/
b2c8950dbc163e2320c742c5badef8d829b836c0
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00067
/
top_fault.v
blob: a601b7c4017beb5b84745244f34b1fc4c14b9823 [
file
]
module
top
(
input en
,
output reg y
);
always
@*
y
=
en
&
!
y
;
endmodule
