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foss-fpga-tools
/
third_party
/
Surelog
/
b2c8950dbc163e2320c742c5badef8d829b836c0
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
expose_evert_dff.ys
blob: a4e825022e0e8c8f4cb89ff5fe92fb80e6dc3704 [
file
]
read_verilog
../
top
.
v
proc
expose
-
evert
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dff
synth
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top top
expose
-
evert
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dff
proc
flatten
opt
opt_rmdff
expose
-
evert
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dff
write_verilog synth
.
v
