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foss-fpga-tools
/
third_party
/
Surelog
/
b2c8950dbc163e2320c742c5badef8d829b836c0
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_map_design.ys
blob: f6fef20e4ed85d9955a0e44e8577ac7c452d4d59 [
file
]
read_verilog
../
top
.
v
design
-
save top_test
extract
-
map
%
top_test
design
-
reset
read_verilog
../
top
.
v
proc
write_verilog synth
.
v
