Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
b2c8950dbc163e2320c742c5badef8d829b836c0
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
shregmap_zinit.ys
blob: cdbf191741bf05768ab1b639c3537fdfdfbfbff6 [
file
]
read_verilog
../
top
.
v
synth_greenpak4
-
run
begin
:
map_luts
shregmap
-
zinit
design
-
reset
read_verilog
../
top
.
v
write_verilog synth
.
v
