Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
b33803e3de1b686792c09675e85fc5f919905e20
/
.
/
src
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sim_clock.ys
blob: 19f31d7a01cd688e5ef587bd284bb354dfe3d572 [
file
] [
log
] [
blame
]
read_verilog
-
sv
../
top
.
v
proc
tee
-
o result
.
log sim
-
clock x top
