Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
b33803e3de1b686792c09675e85fc5f919905e20
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
scripts
/
issue_00175.ys
blob: acbec342e8f84f41475ddbce60216a1d5a10a786 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
hierarchy
proc
opt
memory
opt
fsm
setundef
-
zero
opt
-
full
-
fine
setundef
-
zero
opt
-
full
-
fine
synth
-
top top
write_verilog synth
.
v
