src/Testcases/YosysTests/regression/issue_00350/top.v - third_party/Surelog - Git at Google

 module top (input clk, input i, output o);
   reg q = 0;
   always @(posedge clk) q <= 1;
   assign o = q & i;
 endmodule
	module top (input clk, input i, output o);
	reg q = 0;
	always @(posedge clk) q <= 1;
	assign o = q & i;
	endmodule