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foss-fpga-tools
/
third_party
/
Surelog
/
ba6c8606e9b9f12023a0495454d5f82909d8bb0e
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
issue_00931
/
top.v
blob: 45c84f8bad5bf1544e4c4f87a34df21ac48e81b4 [
file
]
module
top
(
input
[
1
:
0
]
S
,
input
[
7
:
0
]
A
,
B
,
C
,
D
,
output reg
[
7
:
0
]
Y
);
always
@*
begin
case
(
S
)
2
'b00: Y <= A;
2'
b01
:
Y
<=
B
;
2
'b10: Y <= C;
2'
b11
:
Y
<=
D
;
endcase
end
endmodule