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foss-fpga-tools
/
third_party
/
Surelog
/
ba6c8606e9b9f12023a0495454d5f82909d8bb0e
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
issue_01070
/
top.v
blob: 61b64e2c3a3be1c2428416f7f0b90884245119a2 [
file
]
module
top
(
input clk
,
d
,
output reg q
);
wire ce
=
1
'b1;
always @(negedge clk)
if (ce) q <= d;
endmodule
