Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
ba6c8606e9b9f12023a0495454d5f82909d8bb0e
/
.
/
src
/
Testcases
/
YosysTests
/
regression
/
scripts
/
issue_00175.ys
blob: acbec342e8f84f41475ddbce60216a1d5a10a786 [
file
]
read_verilog
../
top
.
v
hierarchy
proc
opt
memory
opt
fsm
setundef
-
zero
opt
-
full
-
fine
setundef
-
zero
opt
-
full
-
fine
synth
-
top top
write_verilog synth
.
v
