blob: fe7cda0745e90c9997563faba245891cc317d60f [file] [log] [blame]
********************************************
* SURELOG System Verilog Compiler/Linter *
********************************************
|-------|------------------|-------------------|
| | FILE UNIT COMP | ALL COMPILATION |
|-------|------------------|-------------------|
| FATAL | 0 | 0 |
| ERROR | 30 | 32 |
|WARNING| 19 | 11 |
| INFO | | |
| NOTE | 12 | 26 |
|-------|------------------|-------------------|
FILE UNIT LOG: ./slpp_unit/surelog.log
ALL FILES LOG: ./slpp_all/surelog.log
DIFFS:
./slpp_unit/work/top_3.v and ./slpp_all/work/top_3.v
./slpp_unit/work/top_4.v and ./slpp_all/work/top_4.v
********************************************
* End SURELOG SVerilog Compiler/Linter *
********************************************
0.94user 0.04system 0:01.17elapsed 84%CPU (0avgtext+0avgdata 49200maxresident)k
656inputs+368outputs (1major+21524minor)pagefaults 0swaps