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foss-fpga-tools
/
third_party
/
Surelog
/
d2ffe725ffd133d54bb69681bb797be77a4d5d40
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01115
/
top.v
blob: 178cd75f6df81759da446392c7f515cb1ee6561b [
file
]
module
top
(
input clk
,
output
[
32
:
0
]
o
);
assign o
=
'bx;
endmodule
