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SVIncCompil
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Testcases
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chapter-6
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6.12--real_bit_select_idx.sv
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/*
:name: real_bit_select
:description: real bit select tests
:should_fail: 1
:tags: 6.12
:type: simulation
*/
module
top
();
real a
=
0.5
;
wire
[
3
:
0
]
b
;
wire c
;
assign c
=
b
[
a
];
endmodule
