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foss-fpga-tools
/
third_party
/
Surelog
/
d4bc91e228686cd8ec9eee019b4f0db9b7bc26cb
/
.
/
SVIncCompil
/
Testcases
/
Icarus
/
ivltests
/
pr735.v
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module
main
;
reg
[
1
:-
10
]
foo
;
initial
begin
foo
=
12
'b0000_0000_0100;
if (foo[-7-1] !== 1'
b1
)
begin
$display
(
"FAILED"
);
$finish
;
end
$display
(
"PASSED"
);
end
endmodule
// main