Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
d4bc91e228686cd8ec9eee019b4f0db9b7bc26cb
/
.
/
SVIncCompil
/
Testcases
/
Yosys
/
lut
/
map_mux.v
blob: ae69404e2854a4f6191b709b7a6c7cb76256d0a5 [
file
]
module
top
();
input a
,
b
,
s
;
output y
;
assign y
=
s
?
a
:
b
;
endmodule