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foss-fpga-tools/third_party/Surelog/d4bc91e228686cd8ec9eee019b4f0db9b7bc26cb/./SVIncCompil/Testcases/YosysBigSim/bch_verilog/sim
tree: 9606ccac05f3762b1c6bb63281d3e8f5c427474a [path history] [tgz]
  1. settings.sh
  2. sim.v
  3. tb_sim.v