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foss-fpga-tools
/
third_party
/
Surelog
/
d4bc91e228686cd8ec9eee019b4f0db9b7bc26cb
/
.
/
SVIncCompil
/
Testcases
/
YosysBigSim
/
verilog-pong
/
sim
/
settings.sh
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YOSYS_COARSE
=
true
TOP
=
"top"
RTL
=
"data.v debounce.v pong_graph.v text_graph.v top.v vga_sync.v"
SIM
=
"bench.v"
