Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
d4bc91e228686cd8ec9eee019b4f0db9b7bc26cb
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_counter_pout.ys
blob: 04bf1d75dd3aefdf7eaa6cacb8d94728878cd285 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
synth_greenpak4
extract_counter
-
pout X
design
-
reset
read_verilog
../
top
.
v
write_verilog synth
.
v