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foss-fpga-tools
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third_party
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Surelog
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d4bc91e228686cd8ec9eee019b4f0db9b7bc26cb
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SVIncCompil
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Testcases
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YosysTests
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simple
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scripts
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shregmap_clkpol_pos.ys
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read_verilog
../
top
.
v
synth_greenpak4
-
run
begin
:
map_luts
shregmap
-
clkpol pos
design
-
reset
read_verilog
../
top
.
v
write_verilog synth
.
v
