src/Testcases/BlackParrot/bp_common/syn/Makefile.verilator

## Tools
CC ?= $(GCC)
VV ?= $(VERILATOR)
PYTHON    ?= python
TRACEDIFF ?= $(BP_COMMON_DIR)/software/tracediff.py

## Tool options
VV_OPTS  = --sc                 # Output in SystemC rather than C++
#VV_OPTS += --debug --gdbbt     # Debugs and produces stack trace
VV_OPTS += -O3

#VV_OPTS += -O1 -fstrict-aliasing # Fastest compile time options

LINT_OPTS   = --lint-only -Wall --Wno-unoptflat 
BUILD_OPTS  = --Wno-fatal --Wno-lint --Wno-style --Wno-widthconcat --Wno-unoptflat --exe -CFLAGS -std=c++11 
BUILD_OPTS += -I$(BP_EXTERNAL_DIR)/share/verilator/include/vltstd/ 
BUILD_OPTS += -LDFLAGS "-L$(BP_EXTERNAL_DIR)/lib -ldramsim -Wl,-rpath=$(BP_EXTERNAL_DIR)/lib"

TOP_MODULE ?= testbench

DUMP ?= 0
COV  ?= 0

.PHONY: dirs.sc lint.sc build.sc run.sc clean.sc

run.sc: sim.sc

VERILATOR_RUN_DIR ?= $(SYN_PATH)/run_verilator

dirs.sc:
	$(eval RESULTS_DIR := $(RESULTS_PATH)/verilator)
	$(eval REPORT_DIR  := $(REPORT_PATH)/verilator)
	$(eval SIM_DIR     := $(RESULTS_DIR)/$(TB).$(CFG).sim/$(PROG))
	$(eval BUILD_DIR   := $(RESULTS_DIR)/$(TB).$(CFG).build)
	$(eval COV_DIR     := $(RESULTS_DIR)/$(TB).$(CFG).cov)
	$(eval LOG_DIR     := $(LOG_PATH)/verilator)

	$(shell mkdir -p $(LOG_DIR))
	$(shell mkdir -p $(REPORT_DIR))

LINT_LOG    ?= $(LOG_DIR)/$(TB).$(CFG).lint.log
LINT_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).lint.rpt
LINT_ERROR  ?= $(REPORT_DIR)/$(TB).$(CFG).lint.err
lint.sc: dirs.sc
	$(shell mkdir -p $(BUILD_DIR))
	$(eval include $(TB_PATH)/$(TB)/Makefile.frag)
	-@sed "s/BP_CFG_FLOWVAR/$(CFG)/g" $(TB_PATH)/$(TB)/testbench.v > $(BUILD_DIR)/testbench.v
	-@sed "s/BP_CFG_FLOWVAR/$(CFG)/g" $(TB_PATH)/$(TB)/wrapper.v > $(BUILD_DIR)/wrapper.v
	-@cat $(SYN_PATH)/lint_settings.verilator | envsubst > $(BUILD_DIR)/config.vlt
	-@cp $(TB_PATH)/$(TB)/test_bp.cpp $(BUILD_DIR)/test_bp.cpp
	-@grep -v -e "^\#" $(SYN_PATH)/flist.verilator       > $(BUILD_DIR)/flist.verilator 
	-@grep -v -e "^\#" $(TB_PATH)/$(TB)/flist.verilator >> $(BUILD_DIR)/flist.verilator
	-@echo $(BUILD_DIR)/wrapper.v                 >> $(BUILD_DIR)/flist.verilator
	-@echo $(BUILD_DIR)/testbench.v               >> $(BUILD_DIR)/flist.verilator
	-@echo $(BUILD_DIR)/test_bp.cpp               >> $(BUILD_DIR)/flist.verilator
	cd $(BUILD_DIR); $(VV) $(LINT_OPTS) --top-module $(TOP_MODULE) \
		config.vlt -f flist.verilator $(HDL_PARAMS) |& tee $(LINT_LOG)


VBUILD_LOG    ?= $(LOG_DIR)/$(TB).$(CFG).vbuild.log
VBUILD_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).vbuild.rpt
VBUILD_ERROR  ?= $(REPORT_DIR)/$(TB).$(CFG).vbuild.err
pre-verilate.sc: dirs.sc
	$(shell mkdir -p $(BUILD_DIR))
	$(eval include $(TB_PATH)/$(TB)/Makefile.frag)
	-@sed "s/BP_CFG_FLOWVAR/$(CFG)/g" $(TB_PATH)/$(TB)/testbench.v > $(BUILD_DIR)/testbench.v
	-@sed "s/BP_CFG_FLOWVAR/$(CFG)/g" $(TB_PATH)/$(TB)/wrapper.v > $(BUILD_DIR)/wrapper.v
	-@cat $(SYN_PATH)/coverage_hier.verilator | envsubst > $(BUILD_DIR)/config.vlt
	-@cp $(TB_PATH)/$(TB)/test_bp.cpp $(BUILD_DIR)/test_bp.cpp
	-@grep -v -e "^\#" $(SYN_PATH)/flist.verilator       > $(BUILD_DIR)/flist.verilator 
	-@grep -v -e "^\#" $(TB_PATH)/$(TB)/flist.verilator >> $(BUILD_DIR)/flist.verilator
	-@echo $(BUILD_DIR)/wrapper.v                 >> $(BUILD_DIR)/flist.verilator
	-@echo $(BUILD_DIR)/testbench.v               >> $(BUILD_DIR)/flist.verilator
	-@echo $(BUILD_DIR)/test_bp.cpp                >> $(BUILD_DIR)/flist.verilator

verilate.sc: pre-verilate.sc
	cd $(BUILD_DIR); $(VV) $(VV_OPTS) $(BUILD_OPTS) --top-module $(TOP_MODULE) \
		config.vlt -f flist.verilator $(HDL_PARAMS) | tee $(VBUILD_LOG)
	-@grep "Error" -A 5 $(VBUILD_LOG) > $(VBUILD_ERROR);
	-@tail -n 2 $(VBUILD_LOG) > $(VBUILD_REPORT)
	-@test -s $(VBUILD_ERROR) && echo "FAILED" >> $(VBUILD_REPORT) \
	|| rm $(VBUILD_ERROR)

CBUILD_LOG    ?= $(LOG_DIR)/$(TB).$(CFG).cbuild.log
CBUILD_REPORT ?= $(LOG_DIR)/$(TB).$(CFG).cbuild.rpt
CBUILD_ERROR  ?= $(LOG_DIR)/$(TB).$(CFG).cbuild.err
build.sc: dirs.sc verilate.sc
	$(MAKE) -C $(BUILD_DIR)/obj_dir -f V$(TOP_MODULE).mk | tee $(CBUILD_LOG)
	-@grep "Error" -A 5 $(CBUILD_LOG) > $(CBUILD_ERROR)
	-@tail -n 2 $(CBUILD_LOG) > $(CBUILD_REPORT)
	-@test -s $(CBUILD_ERROR) && echo "FAILED" >> $(CBUILD_REPORT) \
	|| rm $(CBUILD_ERROR)

ifeq ($(DUMP), 1)
VV_OPTS += --trace         # Dump a VCD
VV_OPTS += --trace-structs # Dump struct information with VCD
VV_OPTS += --trace-depth 10
endif

ifeq ($(COV), 1)
VV_OPTS += --coverage-line
VV_OPTS += --coverage-toggle
endif

sim.sc: SIM_LOG    ?= $(LOG_DIR)/$(TB).$(CFG).sim.$(PROG).log
sim.sc: SIM_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).sim.$(PROG).rpt
sim.sc: SIM_ERROR  ?= $(REPORT_DIR)/$(TB).$(CFG).sim.$(PROG).err
sim.sc: PROG ?= rv64ui-p-simple
sim.sc: COVERAGE_DAT ?= $(PROG)_coverage.dat
sim.sc: dirs.sc 
	$(shell mkdir -p $(SIM_DIR))
	$(shell mkdir -p $(COV_DIR))
	$(eval include $(TB_PATH)/$(TB)/Makefile.frag)
	-@ln -sf $(BUILD_DIR)/obj_dir/V$(TOP_MODULE) $(SIM_DIR)/simsc
	-@cp $(MEM_PATH)/$(PROG).mem $(SIM_DIR)/prog.mem
	-@cp $(MEM_PATH)/$(PROG).riscv $(SIM_DIR)/prog.elf
	-@cp $(MEM_PATH)/$(PROG).dump $(SIM_DIR)/prog.dump
	-@cp $(MEM_PATH)/$(PROG).spike $(SIM_DIR)/prog.spike
	-@cp $(BP_COMMON_DIR)/test/cfg/$(DRAMSIM_CH_CFG) $(SIM_DIR)/dram_ch.ini
	-@cp $(BP_COMMON_DIR)/test/cfg/$(DRAMSIM_SYS_CFG) $(SIM_DIR)/dram_sys.ini
	-@cp $(CCE_MEM_PATH)/$(CCE_MEM) $(SIM_DIR)/cce_ucode.mem
	-cd $(SIM_DIR); ./simsc | tee $(SIM_LOG)
	-@grep "PASS" $(SIM_LOG) || echo "FAILED" > $(SIM_ERROR)
	-@grep "PASS" -A 9 $(SIM_LOG) > $(SIM_REPORT)

match.sc: MATCH_LOG    ?= $(LOG_DIR)/$(TB).$(CFG).match.$(PROG).log
match.sc: MATCH_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).match.$(PROG).rpt
match.sc: MATCH_ERROR  ?= $(REPORT_DIR)/$(TB).$(CFG).match.$(PROG).err
match.sc: PROG ?= rv64ui-p-simple
match.sc: dirs.sc
	-cd $(SIM_DIR); $(PYTHON) $(TRACEDIFF) prog.spike prog.trace $(START_PC) --tolerance=$(TOLERANCE) \
		| tee -a $(MATCH_LOG)
	-@grep "MATCH" $(MATCH_LOG) || echo "MISMATCHED" >> $(MATCH_ERROR)
	-@grep "MATCH" -A 4 $(MATCH_LOG) > $(MATCH_REPORT)

regress_riscv.sc: $(RV64_REGRESSION_SC) 
$(RV64_REGRESSION_SC):
	$(MAKE) sim.sc PROG=$(basename $@)
$(COREMARK_REGRESSION_SC):
	$(MAKE) sim.sc PROG=$(basename $@)
regress_beebs.sc: $(BEEBS_REGRESSION_SC) 
$(BEEBS_REGRESSION_SC):
	$(MAKE) sim.sc PROG=$(basename $@)

$(MC_REGRESSION_SC):
	$(MAKE) sim.sc CFG=$(CFG) PROG=$(basename $@)

cov.sc: COV_LOG    ?= $(LOG_DIR)/$(TB).$(CFG).cov.log
cov.sc: COV_REPORT ?= $(REPORT_DIR)/$(TB).$(CFG).cov.rpt
cov.sc: COV_ERROR  ?= $(REPORT_DIR)/$(TB).$(CFG).cov.err
cov.sc: dirs.sc
	cd $(COV_DIR); \
	verilator_coverage *.dat --rank | tee $(COV_LOG)
	-@cp $(COV_LOG) $(COV_REPORT)

wave.sc: dirs.sc
	cd $(SIM_DIR); $(GTKWAVE) -f dump.vcd &

debug.sc: dirs.sc
	@echo "BlackParrot hardware model does not currently support Verilator VCD dumps"
	exit 1
	$(MAKE) regen -C $(UNHARDWARE_DIR) MODEL=$(UNHARDWARE_MODEL) DATA=$(SIM_DIR)/dump.vcd BINARY=$(SIM_DIR)/prog.elf

clean.sc:
	@rm -rf results/verilator
	@rm -rf reports/verilator
	@rm -rf logs/verilator