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e4de98c2f51ca2a9a11f5ec5c925073e087e1e05
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third_party
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tests
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YosysTests
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regression
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scripts
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issue_00171.ys
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read_verilog
../
top
.
v
proc
;
opt
;
fsm
;
opt
;
memory
;
opt
;
techmap
;
opt
scc
-
all_cell_types
#and then put each found SCC into a module using submod.
scc
-
all_cell_types
synth
-
top top
write_verilog synth
.
v
