Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
e911119afa19222dc9bbad9ba934f3d965e34302
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sat_tempinduct_baseonly.ys
blob: e31f54d0282f07320d84156e8092cff9d58cb759 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
proc
tee
-
o result
.
log sat
-
prove x
1
-
tempinduct
-
baseonly middle