Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
e911119afa19222dc9bbad9ba934f3d965e34302
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sim_clock_mem.ys
blob: bec58e0f6f4230337873d0e809e8010a8da2b753 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
proc
tee
-
o result
.
log sim
-
clock clk top