SVIncCompil/Testcases/YosysTests/regression/scripts/issue_01329.ys - third_party/Surelog - Git at Google

 # read design
 read_verilog ../dff.v
 read_verilog -sv ../synchronizer.sv
 hierarchy -check

 # high-level synthesis
 proc; opt; fsm; opt; memory; opt
 flatten
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 4 t:$adff
 select -assert-count 1 t:$mux
 select -assert-none t:$adff t:$mux %% t:* %D
	# read design
	read_verilog ../dff.v
	read_verilog -sv ../synchronizer.sv
	hierarchy -check

	# high-level synthesis
	proc; opt; fsm; opt; memory; opt
	flatten
	cd dff # Constrain all select calls below inside the top module
	select -assert-count 4 t:$adff
	select -assert-count 1 t:$mux
	select -assert-none t:$adff t:$mux %% t:* %D