blob: 20220f7783c98f3ca9cffdea35f6a378e1bdc0b6 [file] [log] [blame]
[INFO :CM0023] Creating log file ../../../build/tests/YosysBigSimOpenMsp/slpp_unit/surelog.log.
[INFO :CM0020] Separate compilation-unit mode is on.
[WARNI:PP0103] ./rtl/openMSP430_undefines.v:249 Undefining an unknown macro "PMEM_CUSTOM_AWIDTH".
[WARNI:PP0103] ./rtl/openMSP430_undefines.v:250 Undefining an unknown macro "PMEM_CUSTOM_SIZE".
[WARNI:PP0103] ./rtl/openMSP430_undefines.v:251 Undefining an unknown macro "DMEM_CUSTOM_AWIDTH".
[WARNI:PP0103] ./rtl/openMSP430_undefines.v:252 Undefining an unknown macro "DMEM_CUSTOM_SIZE".
[WARNI:PP0103] ./rtl/openMSP430_undefines.v:253 Undefining an unknown macro "PER_CUSTOM_AWIDTH".
[WARNI:PP0103] ./rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE".
[WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell".
[WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset".
[INFO :CP0300] Compilation...
[INFO :CP0303] rtl/omsp_alu.v:1280 Compile module "work@omsp_alu".
[INFO :CP0303] rtl/omsp_clock_module.v:1280 Compile module "work@omsp_clock_module".
[INFO :CP0303] rtl/omsp_dbg.v:1280 Compile module "work@omsp_dbg".
[INFO :CP0303] rtl/omsp_dbg_uart.v:1280 Compile module "work@omsp_dbg_uart".
[INFO :CP0303] rtl/omsp_execution_unit.v:1280 Compile module "work@omsp_execution_unit".
[INFO :CP0303] rtl/omsp_frontend.v:1280 Compile module "work@omsp_frontend".
[INFO :CP0303] rtl/omsp_mem_backbone.v:1280 Compile module "work@omsp_mem_backbone".
[INFO :CP0303] rtl/omsp_multiplier.v:1280 Compile module "work@omsp_multiplier".
[INFO :CP0303] rtl/omsp_register_file.v:1280 Compile module "work@omsp_register_file".
[INFO :CP0303] rtl/omsp_sfr.v:1281 Compile module "work@omsp_sfr".
[INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell".
[INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset".
[INFO :CP0303] rtl/omsp_watchdog.v:1280 Compile module "work@omsp_watchdog".
[INFO :CP0303] rtl/openMSP430.v:1280 Compile module "work@openMSP430".
[INFO :CP0303] sim/bench.v:851 Compile module "work@testbench".
[NOTE :CP0309] rtl/omsp_alu.v:1283 Implicit port type (wire) for "alu_out",
there are 3 more instances of this message.
[NOTE :CP0309] rtl/omsp_clock_module.v:1283 Implicit port type (wire) for "aclk",
there are 14 more instances of this message.
[NOTE :CP0309] rtl/omsp_dbg.v:1283 Implicit port type (wire) for "dbg_cpu_reset",
there are 9 more instances of this message.
[NOTE :CP0309] rtl/omsp_dbg_uart.v:1284 Implicit port type (wire) for "dbg_din",
there are 2 more instances of this message.
[NOTE :CP0309] rtl/omsp_execution_unit.v:1283 Implicit port type (wire) for "cpuoff",
there are 11 more instances of this message.
[NOTE :CP0309] rtl/omsp_frontend.v:1284 Implicit port type (wire) for "decode_noirq",
there are 11 more instances of this message.
[NOTE :CP0309] rtl/omsp_mem_backbone.v:1283 Implicit port type (wire) for "dbg_mem_din",
there are 15 more instances of this message.
[NOTE :CP0309] rtl/omsp_multiplier.v:1283 Implicit port type (wire) for "per_dout".
[NOTE :CP0309] rtl/omsp_register_file.v:1283 Implicit port type (wire) for "cpuoff",
there are 9 more instances of this message.
[NOTE :CP0309] rtl/omsp_sfr.v:1284 Implicit port type (wire) for "cpu_id",
there are 5 more instances of this message.
[NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out".
[NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s".
[NOTE :CP0309] rtl/omsp_watchdog.v:1283 Implicit port type (wire) for "per_dout",
there are 3 more instances of this message.
[NOTE :CP0309] rtl/openMSP430.v:1283 Implicit port type (wire) for "aclk",
there are 25 more instances of this message.
[INFO :EL0526] Design Elaboration...
[NOTE :EL0503] sim/bench.v:851 Top level module "work@testbench".
[NOTE :EL0508] Nb Top level modules: 1.
[NOTE :EL0509] Max instance depth: 5.
[NOTE :EL0510] Nb instances: 18.
[NOTE :EL0511] Nb leaf instances: 9.
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 8
[ NOTE] : 19