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foss-fpga-tools
/
third_party
/
Surelog
/
f013e089f9bd4fcbc5ef193ac9a2a69df4c92505
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01193
/
top.v
blob: 25fc6e76494237a26ad42b7d0de8aa4e38b18f27 [
file
]
module
test
(
input e
,
a
,
output reg b
);
always_comb
if
(
e
)
b
=
a
;
endmodule
