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foss-fpga-tools
/
third_party
/
Surelog
/
f013e089f9bd4fcbc5ef193ac9a2a69df4c92505
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_swap.ys
blob: a3f7cafe32142592f13fd3860700b853956ba638 [
file
]
read_verilog
../
top
.
v
extract
-
map
../
top
.
v
-
swap $dff D
,
CLK
design
-
reset
read_verilog
../
top
.
v
proc
write_verilog synth
.
v
