test update Signed-off-by: Alain <alainmarcel@yahoo.com>
diff --git a/tests/regression.tcl b/tests/regression.tcl index 62e63bd..6776802 100755 --- a/tests/regression.tcl +++ b/tests/regression.tcl
@@ -91,7 +91,6 @@ set LONG_TESTS(YosysOldI2c) 1 set LONG_TESTS(YosysOldI2c) 1 set LONG_TESTS(YosysOldSimpleSpi) 1 -set LONG_TESTS(YosysOldAes) 1 if [regexp {show_diff} $argv] { regsub "show_diff" $argv "" argv
diff --git a/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log b/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log index 365a7af..57b6441 100644 --- a/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log +++ b/third_party/tests/YosysOldTests/aes_core/YosysOldAes.log
@@ -1,73 +1,48 @@ -******************************************** -* SURELOG System Verilog Compiler/Linter * -******************************************** - -[INFO :CM0023] Creating log file ../../../build/tests/YosysOldAes/slpp_unit/surelog.log. +[INFO :CM0023] Creating log file ../../../../build/tests/YosysOldAes/slpp_unit/surelog.log. [INFO :CM0020] Separate compilation-unit mode is on. -[ERROR:PP0101] rtl/aes_inv_sbox.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_sbox.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_rcon.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_key_expand_128.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_inv_cipher_top.v:60 Cannot open include file "timescale.v". - -[ERROR:PP0101] rtl/aes_cipher_top.v:60 Cannot open include file "timescale.v". - -[WARNI:PA0205] cache/synth.v:1 No timescale set for "aes_cipher_top". - -[WARNI:PA0205] cache/synth.v:3293 No timescale set for "aes_key_expand_128". - -[WARNI:PA0205] cache/synth.v:4743 No timescale set for "aes_rcon". - -[WARNI:PA0205] cache/synth.v:4913 No timescale set for "aes_sbox". - -[WARNI:PA0205] rtl/aes_inv_sbox.v:61 No timescale set for "aes_inv_sbox". +[WARNI:PA0205] rtl/aes_cipher_top.v:61 No timescale set for "aes_cipher_top". [WARNI:PA0205] rtl/aes_inv_cipher_top.v:61 No timescale set for "aes_inv_cipher_top". +[WARNI:PA0205] rtl/aes_inv_sbox.v:61 No timescale set for "aes_inv_sbox". + +[WARNI:PA0205] rtl/aes_key_expand_128.v:61 No timescale set for "aes_key_expand_128". + +[WARNI:PA0205] rtl/aes_rcon.v:61 No timescale set for "aes_rcon". + +[WARNI:PA0205] rtl/aes_sbox.v:61 No timescale set for "aes_sbox". + [INFO :CP0300] Compilation... -[INFO :CP0303] cache/synth.v:1 Compile module "work@aes_cipher_top". +[INFO :CP0303] rtl/aes_cipher_top.v:61 Compile module "work@aes_cipher_top". [INFO :CP0303] rtl/aes_inv_cipher_top.v:61 Compile module "work@aes_inv_cipher_top". [INFO :CP0303] rtl/aes_inv_sbox.v:61 Compile module "work@aes_inv_sbox". -[INFO :CP0303] cache/synth.v:3293 Compile module "work@aes_key_expand_128". +[INFO :CP0303] rtl/aes_key_expand_128.v:61 Compile module "work@aes_key_expand_128". -[INFO :CP0303] cache/synth.v:4743 Compile module "work@aes_rcon". +[INFO :CP0303] rtl/aes_rcon.v:61 Compile module "work@aes_rcon". -[INFO :CP0303] cache/synth.v:4913 Compile module "work@aes_sbox". +[INFO :CP0303] rtl/aes_sbox.v:61 Compile module "work@aes_sbox". -[NOTE :CP0309] cache/synth.v:3293 Implicit port type (wire) for "wo_3". +[INFO :CP0302] builtin.sv:4 Compile class "work@mailbox". -[NOTE :CP0309] cache/synth.v:4743 Implicit port type (wire) for "out". +[INFO :CP0302] builtin.sv:33 Compile class "work@process". -[NOTE :CP0309] cache/synth.v:4913 Implicit port type (wire) for "d". +[INFO :CP0302] builtin.sv:58 Compile class "work@semaphore". + +[NOTE :CP0309] rtl/aes_key_expand_128.v:61 Implicit port type (wire) for "wo_0", +there are 3 more instances of this message. [INFO :EL0526] Design Elaboration... -[NOTE :EL0503] cache/synth.v:1 Top level module "work@aes_cipher_top". +[NOTE :EL0503] rtl/aes_cipher_top.v:61 Top level module "work@aes_cipher_top". [NOTE :EL0503] rtl/aes_inv_cipher_top.v:61 Top level module "work@aes_inv_cipher_top". -[WARNI:EL0505] rtl/aes_cipher_top.v:61 Multiply defined module "work@aes_cipher_top", - cache/synth.v:1 previous definition. - -[WARNI:EL0505] timescale.v:2 Multiply defined module "work@aes_key_expand_128", - cache/synth.v:3293 previous definition. - -[WARNI:EL0505] timescale.v:2 Multiply defined module "work@aes_rcon", - cache/synth.v:4743 previous definition. - -[WARNI:EL0505] timescale.v:2 Multiply defined module "work@aes_sbox", - cache/synth.v:4913 previous definition. - [NOTE :EL0504] Multiple top level modules in design. [NOTE :EL0508] Nb Top level modules: 2. @@ -79,13 +54,8 @@ [NOTE :EL0511] Nb leaf instances: 42. [ FATAL] : 0 -[ ERROR] : 6 -[WARNING] : 10 -[ NOTE] : 10 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 6 +[ NOTE] : 8 -******************************************** -* End SURELOG SVerilog Compiler/Linter * -******************************************** - -3.57user 0.06system 0:03.64elapsed 99%CPU (0avgtext+0avgdata 167220maxresident)k -648inputs+616outputs (0major+43425minor)pagefaults 0swaps
diff --git a/third_party/tests/YosysOldTests/aes_core/YosysOldAes.sl b/third_party/tests/YosysOldTests/aes_core/YosysOldAes.sl index 23bd568..78c5e42 100644 --- a/third_party/tests/YosysOldTests/aes_core/YosysOldAes.sl +++ b/third_party/tests/YosysOldTests/aes_core/YosysOldAes.sl
@@ -1 +1 @@ - -writepp -parse -mt max -nopython -fileunit */*.v +incdir+. -nobuiltin -nocache +-parse -fileunit rtl/aes_cipher_top.v rtl/aes_inv_cipher_top.v rtl/aes_inv_sbox.v rtl/aes_key_expand_128.v rtl/aes_rcon.v rtl/aes_sbox.v +incdir+rtl/+. -nocache