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foss-fpga-tools / third_party / Surelog / refs/heads/mithro-patch-1 / . / SVIncCompil / Testcases / YosysDsp
tree: 57231a4a75db6070d1f9979f9a5461ee57216c2d [path history] [tgz]
  1. boxcar.v
  2. delayw.v
  3. dspswitch.v
  4. fastfir.v
  5. fastfir_dynamictaps.v
  6. fastfir_fixedtaps.v
  7. firtap.v
  8. genericfir.v
  9. iiravg.v
  10. lfsr.v
  11. lfsr_fib.v
  12. lfsr_gal.v
  13. README.md
  14. shalfband.v
  15. slowfil.v
  16. slowfil_fixedtaps.v
  17. slowfil_srl.v
  18. slowfil_srl.vh
  19. slowfil_srl_fixedtaps.v
  20. slowsymf.v
  21. smplfir.v
  22. taps.hex
  23. YosysDsp.log
  24. YosysDsp_diff.log
SVIncCompil/Testcases/YosysDsp/README.md

DSP Filters - a selection of digital filters from @ZipCPU

Source: https://github.com/ZipCPU/dspfilters/tree/49b9a0235f88c34b9a997b1aa9a634ad130ea719

Currently three designs exist:

  • fastfir_fixedtaps A 1-output per clock finite impulse response (FIR) filter, configured as a 12-bit 128-tap band-pass filter.

  • slowfil_fixedtaps A 1-output per number-of-taps clocks finite impulse response (FIR) filter, configured as a 12-bit 128-tap band-pass filter. This original variant uses a ring-buffer to store all input samples.

  • slowfil_srl_fixedtaps A 1-output per number-of-taps clocks finite impulse response (FIR) filter, configured as a 12-bit 128-tap band-pass filter. This is a modified variant of the original slowfil that uses a shift-register approach to store all input samples.

The 12-bit 128-tap band pass filter has the following performance characteristics: