Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
refs/heads/mithro-patch-1
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
bigsim
/
navre
tree: c30b2f3b5c2051a70581bac8571b241bbf045918 [
path history
]
[
tgz
]
rtl/
sim/
config
README.md
SVIncCompil/Testcases/YosysTests/bigsim/navre/README.md
The Navré AVR clone (8-bit RISC)
https://opencores.org/project/navre