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foss-fpga-tools/third_party/Surelog/refs/heads/mithro-patch-1/./SVIncCompil/Testcases/YosysTests/bigsim/navre
tree: c30b2f3b5c2051a70581bac8571b241bbf045918
  1. rtl/
  2. sim/
  3. config
  4. README.md
SVIncCompil/Testcases/YosysTests/bigsim/navre/README.md

The Navré AVR clone (8-bit RISC) https://opencores.org/project/navre