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foss-fpga-tools / third_party / Surelog / refs/heads/mithro-patch-1 / . / SVIncCompil / Testcases / Zachjs / relong
tree: 797622a9211e536bab632f37f0a1514f24cd9b3e [path history] [tgz]
  1. alu.sv
  2. alu.v
  3. alu_tb.v
  4. array.sv
  5. array.v
  6. array_tb.v
  7. cache_request.sv
  8. cache_request.v
  9. cache_request_tb.v
  10. case.sv
  11. case.v
  12. case_tb.v
  13. complex_interface.sv
  14. complex_interface.v
  15. complex_interface_tb.v
  16. double_clock.sv
  17. double_clock.v
  18. double_clock_tb.v
  19. enum.sv
  20. enum.v
  21. enum_tb.v
  22. fsm.sv
  23. fsm.v
  24. fsm_tb.v
  25. functions.sv
  26. functions.v
  27. functions_tb.v
  28. gen_struct.sv
  29. gen_struct.v
  30. gen_struct_tb.v
  31. inline_concat.sv
  32. inline_concat.v
  33. inline_concat_tb.v
  34. module_struct.sv
  35. module_struct.v
  36. module_struct_tb.v
  37. port_connections.sv
  38. port_connections.v
  39. port_connections_tb.v
  40. README.md
  41. run.sh
  42. simple_interface.sv
  43. simple_interface.v
  44. simple_interface_tb.v
  45. split_ports.sv
  46. split_ports.v
  47. split_ports_tb.v
  48. split_struct.sv
  49. split_struct.v
  50. split_struct_tb.v
  51. struct.sv
  52. struct.v
  53. struct_tb.v
  54. typedef.sv
  55. typedef.v
  56. typedef_tb.v
SVIncCompil/Testcases/Zachjs/relong/README.md

relong Tests

These tests are borrowed from Reid Long's HDL Examples repository. That repository was intended to provide examples for how the conversions in this project could be done. sv2v does not necessarily convert code as demonstrated in the examples. Notably, sv2v does not create generate blocks when converted vectors with multiple packed dimensions, uses localparams rather than macros for enum conversion, and converts struct literals to concatenations, rather than multiple statements.

Each test case (say, “foo”) is comprised of the following files:

  1. foo.sv: original SystemVerilog
  2. foo.v: hand-converted Verilog
  3. foo_tb.v: basic testbench exercising the given modules

The SystemVerilog source file is converted to Verilog using sv2v, and then both the converted file and the reference Verilog are simulated using Icarus Verilog. This produces VCD files for each which are expected to match exactly, except for the timestamp.

Modifications

The following differences exist between the tests in this folder and their corresponding versions in the source repository.

  1. The inline_concat files were modified to remove a stray trailing semicolon. Though some tools allow for stray semicolons, iverilog does not.
  2. array.v previously had a custom implementation of $clog2, which was removed.
  3. cache_request.sv was modified to include a plain decimal literal to ensure coverage beyond the unbased-unsized literals.
  4. The cache_request2 test is omitted. It was only an example for debugging a VCS-specific issue encountered with cache_request.