| # Surelog |
| System Verilog 2017 Pre-processor, Parser |
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| # Goal |
| This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench. |
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| # Applications |
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| Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter). |
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| # Contributing to this project |
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| This project is open for contribution, any user who needs features built-in or Verilog enthousiast are welcome. |
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| # Features |
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| The preprocessor and the parser use Antlr 4.72 as a parser generator. |
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| The preprocessor and the parser ASTs are made persistent on disk using Google Flatbuffers, enabling incremental compilation. |
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| The tool is built thread safe and performs multithread parsing. |
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| Large files/modules/packages are splitted for multi-threading compilation. |
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| Surelog accepts IEEE Simulator-compliant project specification. |
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| Surelog issues Errors/Warning/Info/Notes about language compliance. |
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| Surelog allows for pre-compiled packages (UVM,...). |
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| # Build instructions and test: |
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| make |
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| # Additional README for more build/test options and system requirements for building: |
| SVIncCompil/README |
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